sl4070b system logic semiconductor sls quad exclusive - or gate high - voltage silicon - gate cmos the sl4070b types consist of four independent exclusive - or gates. the sl4070b provides the system designer with a means for direct implementation of the exlusive - or function. operating voltage range: 3.0 to 18 v maximum input current of 1 m a at 18 v over full package - temperature range; 100 na at 18 v and 25 c noise margin (over full package temp erature range): 1.0 v min @ 5.0 v supply 2.0 v min @ 10.0 v supply 2.5 v min @ 15.0 v supply ordering information SL4070BN plastic sl4070bd soic t a = - 55 to 125 c for all packages logic diagram pin 14 =v cc pin 7 = gnd pin assignment function table inputs output a b y l l l l h h h l h h h l
sl4070b system logic semiconductor sls maximum ratings * sy mbol parameter value unit v cc dc supply voltage (referenced to gnd) - 0.5 to +20 v v in dc input voltage (referenced to gnd) - 0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) - 0.5 to v cc +0.5 v i in dc input current, per pin 10 ma p d power d issipation in still air, plastic dip+ soic package+ 750 500 mw p d power dissipation per output transistor 100 mw tstg storage temperature - 65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plas tic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic pa ckage: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 3.0 18 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types - 55 +125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to th is high - impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
sl4070b system l ogic semiconductor sls dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v 3 - 55 c 25 c 125 c unit v ih minimum high - level input voltage v out =0.5v or v cc - 0.5v v out =1.0v or v cc - 1.0v v out =1.5v or v cc - 1.5 v 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 v v il maximum low - level input voltage v out =0.5v or v cc - 0.5v v out =1.0v or v cc - 1.0v v out =1.5v or v cc - 1.5v 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 v v oh minimum high - level output voltage v in =gnd or v cc 5.0 10 15 4.9 5 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 v v ol maximum low - level output voltage v in =gnd or v cc 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 v i in maximum input leakage current v in = gnd or v cc 18 0.1 0.1 1.0 m a i cc maximum quiescent supp ly current (per package) v in = gnd or v cc 5.0 10 15 20 0.25 0.5 1.0 5.0 0.25 0.5 1.0 5.0 7.5 15 30 150 m a i ol minimum output low (sink) current v in = gnd or v cc u ol =0.4 v u ol =0.5 v u ol =1.5 v 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 ma i oh minim um output high (source) current v in = gnd or v cc u oh =2.5 v u oh =4.6 v u oh =9.5 v u oh =13.5 v 5.0 5.0 10 15 - 2.0 - 0.64 - 1.6 - 4.2 - 1.6 - 0.51 - 1.3 - 3.4 - 1.15 - 0.36 - 0.9 - 2.4 ma
sl4070b system logic semiconductor sls ac electrical characteristics (c l =50pf, r l =200k w , input t r =t f =20 ns) v cc guar anteed limit symbol parameter v 3 - 55 c 25 c 125 c unit t plh , t phl maximum propagation delay, input a or b to output y (figure 1) 5.0 10 15 280 130 100 280 130 100 560 260 200 ns t tlh , t thl maximum output transition time, any output (figure 1) 5.0 10 1 5 200 100 80 200 100 80 400 200 160 ns c in maximum input capacitance - 7.5 pf figure 1. switching waveforms expanded logic diagram (1/4 of the device)
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